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74LVQ10MTR中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

74LVQ10MTR
廠商型號(hào)

74LVQ10MTR

功能描述

TRIPLE 3-INPUT NAND GATE

文件大小

215.25 Kbytes

頁(yè)面數(shù)量

11 頁(yè)

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體(ST)集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二原廠數(shù)據(jù)手冊(cè)到原廠下載

更新時(shí)間

2024-11-8 16:24:00

74LVQ10MTR規(guī)格書詳情

DESCRIPTION

The 74LVQ10 is a low voltage CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

tPD = 5.3ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

ICC = 2μA (MAX.) at TA=25°C

■ LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10

■ IMPROVED LATCH-UP IMMUNITY

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
FAIRCHILD
23+
NA
19960
只做進(jìn)口原裝,終端工廠免費(fèi)送樣
詢價(jià)
ST
22+
14SO
9000
原廠渠道,現(xiàn)貨配單
詢價(jià)
NS
23+
3.9
8920
價(jià)格優(yōu)勢(shì)、原裝現(xiàn)貨、客戶至上。歡迎廣大客戶來(lái)電查詢
詢價(jià)
ST/意法
22+
N/A
354000
詢價(jià)
STMicroelectronics
18+
ICBUSBUFFTRI-STQDLV14SOI
6580
公司原裝現(xiàn)貨
詢價(jià)
ST/意法
23+
SOP
50000
原廠授權(quán)代理,海外優(yōu)勢(shì)訂貨渠道。可提供大量庫(kù)存,詳
詢價(jià)
ST
23+
SOP
16900
正規(guī)渠道,只有原裝!
詢價(jià)
ST
22+
SOP
16900
支持樣品 原裝現(xiàn)貨 提供技術(shù)支持!
詢價(jià)
24+
5000
公司存貨
詢價(jià)
FAIRCHILD/仙童
22+
SOP-14
5623
只做原裝正品現(xiàn)貨!或訂貨假一賠十!
詢價(jià)