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74LVQ20MTR中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

74LVQ20MTR
廠商型號

74LVQ20MTR

功能描述

DUAL 4-INPUT NAND GATE

文件大小

153.41 Kbytes

頁面數(shù)量

8

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體集團(tuán)官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-2-12 22:30:00

74LVQ20MTR規(guī)格書詳情

DESCRIPTION

The 74LVQ20 is a low voltage CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5.3 ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION: ICC = 2μA(MAX.) at TA=25°C

■ LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 20

■ IMPROVED LATCH-UP IMMUNITY

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FAIRCHI
2020+
SOP
80000
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增
詢價
FAI
24+
SMD
20000
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詢價
FSC/ON
23+
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2911
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FAIRCHILD
23+
NA
19960
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詢價
FAI
2018+
SOP20
6528
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詢價
FAIRCHILD
22+23+
SOP
20508
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ST
24+
SOP-20
25843
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ST/意法
23+
NA/
8380
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onsemi(安森美)
23+
QSOP20
7350
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ST
SOP-20
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