8T49N283C-DDDNLGI中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The 8T49N283 has two independent, fractional-feedback PLLs that

can be used as jitter attenuators and frequency translators. It is

equipped with six integer and two fractional output dividers, allowing

the generation of up to 8 different output frequencies, ranging from

8kHz to 1GHz. Four of these frequencies are completely independent

of each other and the inputs. The other four are related frequencies.

The eight outputs may select among LVPECL, LVDS or LVCMOS

output levels.

This makes it ideal to be used in any frequency translation

application, including 1G, 10G, 40G and 100G Synchronous Ethernet,

OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates.

The device may also behave as a frequency synthesizer.

The 8T49N283 accepts up to two differential or single-ended input

clocks and a crystal input. Each of the two internal PLLs can lock to

different input clocks which may be of independent frequencies. Each

PLL can use the other input for redundant backup of the primary

clock, but in this case, both input clocks must be related in frequency.

The device supports hitless reference switching between input

clocks. The device monitors all input clocks for Loss of Signal (LOS),

and generates an alarm when an input clock failure is detected.

Automatic and manual hitless reference switching options are

supported. LOS behavior can be set to support gapped or un-gapped

clocks.

The 8T49N283 supports holdover for each PLL. The holdover has an

initial accuracy of ±50ppB from the point where the loss of all

applicable input reference(s) has been detected. It maintains a

historical average operating point for each PLL that may be returned

to in holdover at a limited phase slope.

The device places no constraints on input to output frequency

conversion, supporting all FEC rates, including the new revision of

ITU-T Recommendation G.709 (2009), most with 0ppm conversion

error.

Each PLL has a register-selectable loop bandwidth from 0.5Hz to

512Hz.

Each output supports individual phase delay settings to allow

output-output alignment.

The device supports Output Enable inputs and Lock, Holdover and

LOS status outputs.

The device is programmable through an I2C interface. It also supports

I

2C master capability to allow the register configuration to be read

from an external EEPROM.

Features

? Supports SDH/SONET and Synchronous Ethernet clocks

including all FEC rate conversions

? Two differential outputs meet jitter limits for 100G Ethernet and

STM-256/OC-768

? <0.3ps RMS (including spurs): 12kHz to 20MHz

? All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz

? Operating modes: locked to input signal, holdover and free-run

? Initial holdover accuracy of ±50ppb

? Accepts up to two LVPECL, LVDS, LVHSTL or LVCMOS input

clocks

? Accepts frequencies ranging from 8kHz up to 875MHz

? Auto and manual input clock selection with hitless switching

? Clock input monitoring, including support for gapped clocks

? Phase-Slope Limiting and Fully Hitless Switching options to

control output phase transients

? Operates from a 10MHz to 40MHz fundamental-mode crystal

? Generates eight LVPECL / LVDS or sixteen LVCMOS output

clocks

? Output frequencies ranging from 8kHz up to 1.0GHz (diff)

? Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

? Four General Purpose I/O pins with optional support for status &

control:

? Four Output Enable control inputs may be mapped to any of the

eight outputs

? Lock, Holdover & Loss-of-Signal status outputs

? Open-drain Interrupt pin

? Programmable PLL bandwidth settings for each PLL:

? 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz

or 512Hz

? Optional Fast Lock function

? Programmable output phase delays in steps as small as 16ps

? Register programmable through I2C or via external I2C EEPROM

? Bypass clock paths for system tests

? Power supply modes

VCC / VCCA / VCCO

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

? Power down modes support consumption as low as 1.7W (see

Power Dissipation and Thermal Considerations for details)

? -40°C to 85°C ambient operating temperature

? Package: 56QFN, lead-free (RoHS 6)