首頁(yè)>A67L0636E-3.2>規(guī)格書(shū)詳情
A67L0636E-3.2中文資料歐密格數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
A67L0636E-3.2規(guī)格書(shū)詳情
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L1618, A67L0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.
Features
■ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
■ Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization
■ Signal +3.3V ± 5 power supply
■ Individual Byte Write control capability
■ Clock enable ( CEN) pin to enable clock and suspend operations
■ Clock-controlled and registered address, data and control signals
■ Registered output for pipelined applications
■ Three separate chip enables allow wide range of options for CE control, address pipelining
■ Internally self-timed write cycle
■ Selectable BURST mode (Linear or Interleaved)
■ SLEEP mode (ZZ pin) provided
■ Available in 100 pin LQFP package
產(chǎn)品屬性
- 型號(hào):
A67L0636E-3.2
- 制造商:
AMICC
- 制造商全稱:
AMIC Technology
- 功能描述:
2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
AMICC |
23+ |
原廠原包 |
19960 |
只做進(jìn)口原裝 終端工廠免費(fèi)送樣 |
詢價(jià) |