AD1836AASZRL集成電路（IC）的編解碼器規(guī)格書PDF中文資料

AD1836AASZRL屬于集成電路（IC）的編解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD1836AASZRL編解碼器編解碼器是用于通過壓縮和解壓縮來轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲空間。某些編解碼器提供高達(dá) 32 位的分辨率，并且分別提供多達(dá) 6 個或 8 個模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。

PRODUCT OVERVIEW

The AD1836A is a high performance, single-chip codec that provides three stereo DACs and two stereo ADCs using Analog Devices, Inc., patented multibit Σ-Δ architecture. An SPI? port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1836A operates from a 5 V supply, with provision for a separate output supply to interface with low voltage external circuitry. The AD1836A is available in a 52-lead MQFP (PQFP) package.

FEATURES

5 V multichannel audio system

Accepts 16-/18-/20-/24-bit data

Supports 24-bit and 96 kHz sample rate

Multibit Σ-? modulators with data directed

scrambling

Differential output for optimum performance

ADCs: –92 dB THD + N, 105 dB SNR and dynamic range

DACs: –95 dB THD + N, 108 dB SNR and dynamic range

On-chip volume control with auto-ramp function

Programmable gain amplifier for ADC input

Hardware and software controllable clickless mute

Digital de-emphasis processing

Supports 256 × fS, 512 × fS, or 768 × fS master clock

Power-down mode plus soft power-down mode

Flexible serial data port with right justified, left justified, I2S

compatible, and DSP serial port modes

TDM interface mode supports 8 in/8 out using a single

SHARC? SPORT

52-lead MQFP (PQFP) plastic package

APPLICATIONS

Home theater systems

Automotive audio systems

DVD recorders

Set-top boxes

Digital audio effects processors