AD7264BCPZ集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD7264BCPZ屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD7264BCPZ模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進(jìn)行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進(jìn)制補(bǔ)碼二進(jìn)制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進(jìn)行選擇。

GENERAL DESCRIPTION

The AD7264 is a dual, 14-bit, high speed, low power, successive approximation ADC that operates from a single 5 V power supply and features throughput rates of up to 1 MSPS per on-chip ADC (500 kSPS for the AD7264-5). Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.

FEATURES

Dual, simultaneous sampling, 14-bit, 2-channel ADC

True differential analog inputs

Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,

×24, ×32, ×48, ×64, ×96, ×128

Throughput rate per ADC

1 MSPS for AD7264

500 kSPS for AD7264-5

Analog input impedance: >1 GΩ

Wide input bandwidth

?3 dB bandwidth: 1.7 MHz at gain = 2

4 on-chip comparators

SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32

Device offset calibration

System gain calibration

On-chip reference: 2.5 V

?40°C to +105°C operation

High speed serial interface

Compatible with SPI, QSPI?, MICROWIRE?, and DSP

48-lead LFCSP and LQFP packages