AD8159集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書(shū)PDF中文資料

AD8159屬于集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD8159信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開(kāi)關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類(lèi)似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無(wú)窮變化量。

GENERAL DESCRIPTION

The AD8159 is an asynchronous, protocol agnostic, quad-lane 2:1 switch with a total of 12 differential PECL/CML-compatible inputs and 12 differential CML outputs. The operation of this product is optimized for NRZ signaling with data rates up to 3.2 Gbps per lane. Each lane offers two levels of input equalization and four levels of output pre-emphasis.

FEATURES

Port level 2:1 mux/1:2 demux

Each port consists of 4 lanes

Each lane runs from dc to 3.2 Gbps, independent of the other lanes

Compensates over 40 inches of FR4 at 3.2 Gbps through two levels of input equalization, or four levels of output pre-emphasis

Accepts ac- or dc-coupled differential CML inputs

Low deterministic jitter, typically 20 ps p-p

Low random jitter, typically 1 ps rms

BER < 10-16

On-chip termination

Reversible inputs and outputs on one port

Unicast or bicast on 1:2 demux function

Port level loopback capability

Single lane switching capability

3.3 V core supply

Flexible I/O supply down to 2.5 V

Low power, typically 1 W in basic configuration

100-pin TQFP_EP

?40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch

SONET OC48/SDH16 and lower data rates

XAUI (10 Gigabit Ethernet) over backplane

Gigabit Ethernet over backplane

Fibre channel 1.06 Gbps and 2.125 Gbps over backplane

Infiniband over backplane

PCI-Express over backplane