AD8155ACPZ集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

AD8155ACPZ屬于集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD8155ACPZ信號開關(guān)，多路復(fù)用器，解碼器邏輯型信號開關(guān)、多路復(fù)用器和編碼器 IC 可用于對以數(shù)字格式表示數(shù)據(jù)的電信號進行路由和選擇。這些器件與設(shè)計用于模擬信號的類似產(chǎn)品有所不同，它們保留的信息表示為兩個電狀態(tài)之一，而不是兩個外部界限內(nèi)的無窮變化量。

GENERAL DESCRIPTION

The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output preemphasis, programmable output levels, and loss-of-signal detection.

The nonblocking switch core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew.

FEATURES

Dual 2:1 mux/1:2 demux

Optimized for dc to 6.5 Gbps NRZ data

Per-lane P/N pair inversion for routing ease

Programmable input equalization

Compensates up to 40 inches of FR4

Loss-of-signal detection

Programmable output preemphasis up to 12 dB

Programmable output levels with squelch and disable

Accepts ac-coupled or dc-coupled differential CML inputs

50 Ω on-chip termination

1:2 demux supports unicast or bicast operation

Port-level loopback

Port or single lane switching

1.8 V to 3.3 V flexible core supply

User-settable I/O supply from VCC to 1.2 V

Low power, typically 2.0 W in basic configuration

64-lead LFCSP

?40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch

SONET OC48/SDH16 and lower data rates

RXAUI, 4× Fibre Channel, Infiniband, and GbE over

backplane

OIF CEI 6.25 Gbps over backplane

Serial data-level shift

2-/4-/6-lane equalizers or redrivers