AD9508PCBZ中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements.

There are four independent differential clock outputs, each with various types of logic levels available. Available logic types include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS (250 MHz). In 1.8 V CMOS output mode, the differential output becomes two CMOS single-ended signals. The CMOS outputs are 1.8 V logic levels, regardless of the operating supply voltage.

FEATURES

1.65 GHz differential clock inputs/outputs

10-bit programmable dividers, 1 to 1024, all integers

Up to 4 differential outputs or 8 CMOS outputs

Pin strapping capability for hardwired programming at

power-up

<115 fs rms broadband random jitter (see Figure 25)

Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)

Excellent output-to-output isolation

Automatic synchronization of all outputs

Single 2.5 V/3.3 V power supply

Internal LDO (low drop-out) voltage regulator for enhanced

power supply immunity

Phase offset select for output-to-output coarse delay adjust

3 programmable output logic levels, LVDS, HSTL, and CMOS

Serial control port (SPI/I2C) or pin-programmable mode

Space-saving 24-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure