AD9524/PCBZ開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件規(guī)格書PDF中文資料

AD9524/PCBZ屬于開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9524/PCBZ評(píng)估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過(guò)驗(yàn)證的實(shí)施環(huán)境中評(píng)估某些重點(diǎn)器件的性能或特性。評(píng)估方法通常有完善的文檔說(shuō)明，并且視乎具體情況由評(píng)估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對(duì)于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開(kāi)關(guān)模式電源)，評(píng)估平臺(tái)可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

GENERAL DESCRIPTION

The AD9524 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. The AD9524 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise require ments necessary for acceptable data converter SNR performance.

FEATURES

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)

Zero delay operation

Input-to-output edge timing: <±150 ps

6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

6 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ? period of VCO output divider

Output-to-output skew: <±50 ps

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: ?160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I2C-compatible serial control port

Dual PLL architecture

PLL1

Low bandwidth for reference input clock cleanup with external VCXO

Phase detector rate of 300 kHz to 75 MHz

Redundant reference inputs

Auto and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF synthesizers

PLL2

Phase detector rate of up to 250 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation