AD9550/PCBZ開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件規(guī)格書(shū)PDF中文資料

AD9550/PCBZ屬于開(kāi)發(fā)板套件編程器的評(píng)估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9550/PCBZ評(píng)估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過(guò)驗(yàn)證的實(shí)施環(huán)境中評(píng)估某些重點(diǎn)器件的性能或特性。評(píng)估方法通常有完善的文檔說(shuō)明，并且視乎具體情況由評(píng)估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對(duì)于數(shù)量特別多或類(lèi)別獨(dú)特的器件類(lèi)別(如 ADC、DAC 和開(kāi)關(guān)模式電源)，評(píng)估平臺(tái)可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

GENERAL DESCRIPTION

The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input.

FEATURES

Converts preset standard input frequencies to standard

output frequencies

Input frequencies from 8 kHz to 200 MHz

Output frequencies up to 810 MHz LVPECL and LVDS

(200 MHz CMOS)

Preset pin-programmable frequency translation ratios

On-chip VCO

Single-ended CMOS reference input

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer

and tolerance specifications

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Flexible frequency translation for wireline applications such

as Ethernet, T1/E1, SONET/SDH, GPON, xDSL

Wireless infrastructure

Test and measurement (including handheld devices)