AD9553BCPZ集成電路（IC）的應(yīng)用特定時鐘/定時規(guī)格書PDF中文資料

AD9553BCPZ屬于集成電路（IC）的應(yīng)用特定時鐘/定時。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9553BCPZ應(yīng)用特定時鐘/定時專用時鐘和計(jì)時 IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

GENERAL DESCRIPTION

The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.

FEATURES

Input frequencies from 8 kHz to 710 MHz

Output frequencies up to 810 MHz LVPECL and LVDS (up to

200 MHz for CMOS output)

Preset pin-programmable frequency translation ratios cover

popular wireline and wireless frequency applications,

including xDSL, T1/E1, BITS, SONET, and Ethernet

Arbitrary frequency translation ratios via SPI port

On-chip VCO

Accepts a crystal resonator for holdover applications

Two single-ended (or one differential) reference input(s)

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

SPI-compatible, 3-wire programming interface

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer,

and tolerance specifications

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Extremely flexible frequency translation for SONET/SDH,

Ethernet, Fibre Channel, DRFI/DOCSIS, and

PON/EPON/GPON

Wireless infrastructure

Test and measurement (including handheld devices)