GENERAL DESCRIPTION

The ADSP-21467/ADSP-21469 SHARC? processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (singleinstruction, single-data) mode. These 32-bit/40-bit floatingpoint processors are optimized for high performance audio applications with their large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications/peripheral interfaces (DAI/DPI).

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM

Up to 450 MHz operating frequency

Qualified for automotive applications, see Automotive

Products on Page 74

Code compatible with all other members of the SHARC family

Available with unique audiocentric peripherals such as the

digital applications interface, DTCP (digital transmission

content protection protocol), serial ports, precision clock

generators, S/PDIF transceiver, asynchronous sample rate

converters, input data port, and more.

For complete ordering information, see Ordering Guide on

Page 74

ADSP-21469BBCZ-3屬于集成電路（IC） > DSP（數(shù)字信號(hào)處理器）。亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-21469BBCZ-3DSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類(lèi)似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。