ATF1508AS-10JC84集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書PDF中文資料

Description

The ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications.

Features

? High-density, High-performance, Electrically-erasable Complex Programmable Logic Device

– 128 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 84, 100, 160 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

? Flexible Logic Macrocell

– D/T/Latch Configured Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

? Advanced Power Management Features

– Automatic 10 μA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

? Available in Commercial and Industrial Temperature Ranges

? Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages

? Advanced EE Technology

– 100 Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

? JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

? Fast In-System Programmability (ISP) via JTAG

? PCI-compliant

? 3.3 or 5.0V I/O Pins

? Security Fuse Feature

? Green (Pb/Halide-free/RoHS Compliant) Package Options

Enhanced Features

? Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

? Output Enable Product Terms

? Transparent-latch Mode

? Combinatorial Output with Registered Feedback within Any Macrocell

? Three Global Clock Pins

? ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

? Fast Registered Input from Product Term

? Programmable “Pin-keeper” Option

? VCC Power-up Reset Option

? Pull-up Option on JTAG Pins TMS and TDI

? Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts