CY2309C集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309. The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

■10 MHz to 100–133 MHz operating range

■Zero input and output propagation delay

■Multiple low skew outputs

■One input drives five outputs (CY2305C)

■One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)

■50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)