CY7C1212H中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description[1]

The CY7C1212H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Features

? Registered inputs and outputs for pipelined operation

? 64K × 18 common I/O architecture

? 3.3V core power supply (VDD)

? 2.5V/3.3V I/O power supply (VDDQ)

? Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

? Provide high-performance 3-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed write

? Asynchronous output enable

? Available in JEDEC-standard lead-free 100-Pin TQFP package

? “ZZ” Sleep Mode Option