CY7C1300A中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.

The CY7C1300A allows the user to concurrently perform Reads, Writes, or pass-through cycles in combination on the two data ports. The two address ports (AX, AY) determine the Read or Write locations for their respective data ports (DQX, DQY).

Features

? Fast clock speed: 100 and 83 MHz

? Fast access times: 5.0/6.0 ns max.

? Single clock operation

? Single 3.3V –5 and +5 power supply VCC

? Separate VCCQ for output buffer

? Two chip enables for simple depth expansion

? Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX, PTY, WEX, WEY, and data output registers on-chip

? Concurrent Reads and Writes

? Two bidirectional data buses

? Can be configured as separate I/O

? Pass-through feature

? Asynchronous output enables (OEX, OEY)

? LVTTL-compatible I/O

? Self-timed Write

? Automatic power-down

? 176-pin TQFP package