CY7C1312V18中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR?-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Features

? Separate Independent Read and Write Data Ports

— Supports concurrent transactions

? 167-MHz Clock for High Bandwidth

? Two-word Burst on all accesses

? Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @ 167MHz

? Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

? Two output clocks (C and C) accounts for clock skew and flight time mismatches

? Echo clocks (CQ and CQ) simplify data capture in high speed systems

? Single multiplexed address input bus latches address inputs for both Read and Write ports

? Separate Port Selects for depth expansion

? Synchronous internally self-timed writes

? Available in x8, x18, and x36 configurations

? 1.8V core power supply with HSTL Inputs and Outputs

? 13x15 mm 1.0-mm pitch FBGA package, 165 ball (11x15 matrix)

? Variable drive HSTL output buffers

? Extended HSTL output voltage (1.4V–VDD)

? JTAG Interface

? On-chip Delay Lock Loop (DLL)