CY7C1313AV18-167BZC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or 36-bit words (CY7C1315AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Features

? Separate Independent Read and Write Data Ports

— Supports concurrent transactions

? 250-MHz Clock for High Bandwidth

? 4-Word Burst for reducing address bus frequency

? Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz

? Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

? Two output clocks (C and C) accounts for clock skew and flight time mismatching

? Echo clocks (CQ and CQ) simplify data capture in high speed systems

? Single multiplexed address input bus latches address inputs for both Read and Write ports

? Separate Port Selects for depth expansion

? Synchronous internally self-timed writes

? Available in ×8, ×18, and ×36 configurations

? Full data coherancy providing most current data

? Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)

? 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix)

? Variable drive HSTL output buffers

? JTAG 1149.1 Compatible test access port

? Delay Lock Loop (DLL) for accurate data placement