CY7C1347G-133AXC集成電路（IC）的存儲器規(guī)格書PDF中文資料

Functional Description

The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC?. The burst sequence is selected through the MODE pin.

Features

? Fully registered inputs and outputs for pipelined operation

? 128K x 36 common IO architecture

? 3.3V core power supply (VDD)

? 2.5V/3.3V I/O power supply (VDDQ)

? Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? Offered in lead-free 100-Pin TQFP, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package

? “ZZ” sleep mode option and stop clock option

? Available in industrial and commercial temperature ranges