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CY7C1353

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353isa3.3V256Kby18Synchronous-Flow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353isequippedwiththeadvancedNoBusLatency(NoBL?)logicrequiredto

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353-40AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353isa3.3V256Kby18Synchronous-Flow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353isequippedwiththeadvancedNoBusLatency(NoBL?)logicrequiredto

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353-50AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353isa3.3V256Kby18Synchronous-Flow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353isequippedwiththeadvancedNoBusLatency(NoBL?)logicrequiredto

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353-66AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353isa3.3V256Kby18Synchronous-Flow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353isequippedwiththeadvancedNoBusLatency(NoBL?)logicrequiredto

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-100AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-117AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-40AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-50AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-50BGC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-66AC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353B-66BGC

256Kx18 Flow-Through SRAM with NoBL Architecture

FunctionalDescription TheCY7C1353Bisa3.3V,256Kby18SynchronousFlow-ThroughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353BisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-100AC

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-100AI

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-117AC

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-117AI

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-133AC

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-133AI

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

CY7C1353F-66AC

4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

FunctionalDescription[1] TheCY7C1353Fisa3.3V,256Kx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1353FisequippedwiththeadvancedNoBusLatency?(NoBL?)logicrequi

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導體公司

詳細參數(shù)

  • 型號:

    CY7C1353

  • 制造商:

    CYPRESS

  • 功能描述:

    *

供應商型號品牌批號封裝庫存備注價格
CYPR
23+
TQFP
9526
詢價
CYPRESS
00+/01+
QFP
157
全新原裝100真實現(xiàn)貨供應
詢價
Cypress
Cypress專業(yè)分銷
1500
Cypress一級分銷,原裝原盒原包裝!
詢價
CYP
2001
7
原裝正品現(xiàn)貨庫存價優(yōu)
詢價
CYPRESS
2016+
QFP100
5500
只做原裝,假一罰十,公司可開17%增值稅發(fā)票!
詢價
CYPRESS
24+
QFP
1503
詢價
CYP
23+
貼片
5000
原裝正品,假一罰十
詢價
CYPRESS
2016+
QFP100P
6523
只做原裝正品現(xiàn)貨!或訂貨!
詢價
CYPRESS
05+
QFP
500
詢價
CYP
2339+
N/A
5650
公司原廠原裝現(xiàn)貨假一罰十!特價出售!強勢庫存!
詢價
更多CY7C1353供應商 更新時間2025-1-7 17:09:00