CY7C1485V33中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description[1]

The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Features

? Supports bus operation up to 250 MHz

? Available speed grades are 250, 200, and 167 MHz

? Registered inputs and outputs for pipelined operation

? Optimal for performance (double cycle deselect)

? Depth expansion without wait state

? 3.3V core power supply (VDD)

? 2.5V/3.3V IO operation

? Fast clock-to-output times

— 3.0 ns (for 250 MHz device)

? Provide high performance 3-1-1-1 access rate

? User selectable burst counter supporting Intel?

Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self timed writes

? Asynchronous output enable

? CY7C1484V33, CY7C1485V33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package

? IEEE 1149.1 JTAG-Compatible Boundary Scan

? “ZZ” Sleep Mode option