CY7C1486BV33中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

■ 2.5 V/3.3 V I/O operation

■ Fast clock-to-output times

? 3.0 ns (for 250 MHz device)

■ Provide high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed writes

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1480BV33, CY7C1482BV33 available in JEDEC standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball fine-pitch ball grid array (FBGA) package. CY7C1486BV33 available in Pb-free and non-Pb-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-compatible boundary scan

■ “ZZ” sleep mode option