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CY7C1512KV18-300BZXC集成電路(IC)的存儲器規(guī)格書PDF中文資料
廠商型號 |
CY7C1512KV18-300BZXC |
參數(shù)屬性 | CY7C1512KV18-300BZXC 封裝/外殼為165-LBGA;包裝為卷帶(TR);類別為集成電路(IC)的存儲器;產品描述:IC SRAM 72MBIT PARALLEL 165FBGA |
功能描述 | 72-Mbit QDR-II SRAM 2-Word Burst Architecture |
文件大小 |
814.94 Kbytes |
頁面數(shù)量 |
30 頁 |
生產廠商 | CypressSemiconductor |
企業(yè)簡稱 |
Cypress【賽普拉斯】 |
中文名稱 | 賽普拉斯半導體公司官網 |
原廠標識 | |
數(shù)據(jù)手冊 | |
更新時間 | 2024-12-25 14:42:00 |
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CY7C1512KV18-300BZXC規(guī)格書詳情
Functional Description
The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.
Features
■ Separate Independent Read and Write Data Ports
? Supports concurrent transactions
■ 333 MHz Clock for High Bandwidth
■ 2-word Burst on all Accesses
■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 666 MHz) at 333 MHz
■ Two Input Clocks (K and K) for precise DDR timing
? SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
■ Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports
■ Separate Port Selects for Depth Expansion
■ Synchronous internally Self-timed Writes
■ QDR?-II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
■ Operates similar to QDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing Most Current Data
■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
? Supports both 1.5V and 1.8V IO supply
■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable Drive HSTL Output Buffers
■ JTAG 1149.1 Compatible Test Access Port
■ Phase Locked Loop (PLL) for Accurate Data Placement
產品屬性
- 產品編號:
CY7C1512KV18-300BZXC
- 制造商:
Cypress Semiconductor Corp
- 類別:
集成電路(IC) > 存儲器
- 包裝:
卷帶(TR)
- 存儲器類型:
易失
- 存儲器格式:
SRAM
- 技術:
SRAM - 同步,QDR II
- 存儲容量:
72Mb(4M x 18)
- 存儲器接口:
并聯(lián)
- 電壓 - 供電:
1.7V ~ 1.9V
- 工作溫度:
0°C ~ 70°C(TA)
- 安裝類型:
表面貼裝型
- 封裝/外殼:
165-LBGA
- 供應商器件封裝:
165-FBGA(13x15)
- 描述:
IC SRAM 72MBIT PARALLEL 165FBGA
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
CYPRESS |
23+ |
FBGA |
44261 |
公司原裝現(xiàn)貨!主營品牌!可含稅歡迎查詢 |
詢價 | ||
CY |
24+ |
BGA |
23000 |
免費送樣原盒原包現(xiàn)貨一手渠道聯(lián)系 |
詢價 | ||
Cypress |
165-FBGA |
3260 |
Cypress一級分銷,原裝原盒原包裝! |
詢價 | |||
CYPRESS |
2018+ |
BGA |
6528 |
承若只做進口原裝正品假一賠十! |
詢價 | ||
CYPRESS/賽普拉斯 |
2315+ |
BGA |
3668 |
優(yōu)勢代理渠道,原裝現(xiàn)貨,可全系列訂貨 |
詢價 | ||
SPANSION(飛索) |
2021+ |
FBGA-165(13x15) |
499 |
詢價 | |||
CYPRESS/賽普拉斯 |
2022 |
NA |
80000 |
原裝現(xiàn)貨,OEM渠道,歡迎咨詢 |
詢價 | ||
CYPRESS |
22+ |
BGA |
21153 |
原裝正品現(xiàn)貨 |
詢價 | ||
CYPRESS/賽普拉斯 |
21+ |
BGA |
1062 |
只做原裝正品,不止網上數(shù)量,歡迎電話微信查詢! |
詢價 | ||
CYPRESS/賽普拉斯 |
22+ |
BGA |
18000 |
原裝正品 |
詢價 |