CYP15G0402DX集成電路（IC）的電信規(guī)格書PDF中文資料

Functional Description

The CYP15G0402DX Quad HOTLinkII? SERDES is a point-to-point communications building block allowing the transfer of pre-encoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging from 200 to 1500 MBaud per serial link.

Each transmit channel accepts pre-encoded 10-bit transmission characters in an input register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, frames these characters to the proper 10-bit character boundaries, and this data becomes register outputs with a recovered character clock. Figure 1 illustrates typical connections between independent systems and a CYP15G0402DX.

As a second-generation HOTLink device, the CYP15G0402DX extends the HOTLink family to faster data rates, while maintaining serial link compatibility with other HOTLink devices.

Features

? Second generation HOTLink? technology

? Fibre-Channel and Gigabit-Ethernet-compliant

? 10-bit unencoded data transport

— Aggregate throughput of 12 GB/s

? Selectable parity check/generate

? Four independently controlled 10-bit channels

? Selectable input clocking options

? User selectable framing character

— +Comma, ±comma, or full K28.5 detect

— Single or multicharacter framer for character alignment

— Low-latency option

? Synchronous parallel input interface

— User-configurable threshold level

— Compatible with LVTTL, LVCMOS, LVTTL

? Synchronous parallel output interface

— Compatible with LVTTL, LVCMOS, LVTTL

? 200-to-1500 MBaud serial signaling rate

? Internal PLLs with no external PLL components

— Separate clock and data-recovery PLL per channel

— Common transmit clock multiplier PLL

? Differential PECL-compatible serial inputs

? Differential PECL-compatible serial outputs

— Source matched for 50? transmission lines

— No external resistors required

— Adjustable amplitude for 100? or 150? balanced loads

? Compatible with fiber-optic modules and copper cables

? JTAG boundary scan

? Built-in self-test (BIST) for at-speed link testing

? Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

? Low-power 3W typical

? 256-ball BGA

? 0.25μ BiCMOS technology