CYT2CLHBAAQ0AZSGS中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

? Dual CPU subsystem

- 160-MHz (max) 32-bit Arm? Cortex?-M4F CPU with

? Single-cycle multiply

? Single-precision floating point unit (FPU)

? Memory protection unit (MPU)

- 100-MHz (max) 32-bit Arm? Cortex?-M0+ CPU with

? Single-cycle multiply

? Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

? Peripheral DMA controller #0 (P-DMA0) with 76 channels

? Peripheral DMA controller #1 (P-DMA1) with 84 channels

? Memory DMA controller #0 (M-DMA0) with 4 channels

? Integrated memories

- Up to 4160 KB of code-flash with an additional 128 KB of work-flash

? Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it

? Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

? Flash programming through SWD/JTAG interface

- Up to 512 KB of SRAM with selectable retention granularity

? Crypto engine[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

? Using digital signature verification

? Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

? Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detector (BOD)

- Overvoltage detection (OVD)

- Clock supervisor (CSV)

? Supported in all power modes

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)

? Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

? Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA_ADC

? One threshold level (1.1 V) for BOD on VCCD

? Wakeup support

- Up to four pins to wakeup from Hibernate mode

- Wakeup recognition bit for each wakeup source

- Up to 128 GPIO pins to wakeup from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

? Clock sources

- Internal main oscillator (IMO)

- Internal low-speed oscillator (ILO)

- External crystal oscillator (ECO)

- Watch crystal oscillator (WCO)

- Phase-locked loop (PLL)

- Frequency-locked loop (FLL)

- Low-power external crystal oscillator (LPECO)

? LCD controller

- Up to four LCD controllers, with 32 segments (SEG) and four commons (COM)

- Supports both Type A (standard) and Type B (low-power) drive waveforms

- Three drive modes

? PWM drive at 1/2 bias

? PWM drive at 1/3 bias

? Digital correlation

- Operates in ACTIVE, SLEEP, and DeepSleep power modes

- Digital contrast control

? Sound subsystem

- Two time-division multiplexing (TDM) interfaces

- Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces

- Up to five sound generator (SG) interfaces

- One PCM Audio stream mixer with five input streams

? Communication interfaces

- Up to four CAN FD channels

? Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

? Compliant to ISO 11898-1:2015

? Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

? ISO 16845:2015 certificate available

- Up to 12 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,

or UART

- Up to two independent LIN channels

? LIN protocol compliant with ISO 17987

- Up to two CXPI channels with data rate up to 20 kbps

? Serial memory interface (SMIF)

- One SPI (single, dual, quad, or octal), xSPI interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

? Timers

- Up to 46 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks for regular operations

? Up to 12 16-bit counters optimized for motor-control operations (Equivalent to 6 stepper motor-control

[SMC] channels with ZPD and slew rate control capability)

? Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_

DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

? Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

? Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- Supports both 12- and 24-hour formats

- Automatic leap-year correction

? I/O

- Up to 140 Programmable I/Os

- Two I/O types

? GPIO Standard (GPIO_STD)

? GPIO Enhanced (GPIO_ENH)

? GPIO Stepper Motor Control (GPIO_SMC)

? High-Speed I/O Standard with Low Noise (HSIO_STDLN)

? Regulators

- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Two types of regulators

? DeepSleep

? Core internal

? Programmable analog

- One SAR A/D converter

? Each ADC supports 32 logical channels, with 48 external channels. Any external channel can be connected

to any logical channel in the SAR.

? 12-bit resolution and sampling rates up to 1 Msps

- The ADC also supports six internal analog inputs like:

? Bandgap reference to establish absolute voltage levels

? Calibrated diode for junction temperature calculations

? Two AMUXBUS inputs and two direct connections to monitor supply levels

- ADC supports addressing of external multiplexers

- ADC has a sequencer supporting autonomous scanning of configured channels

? Smart I/O

- One smart I/O block, which can perform Boolean operations on signals going to and from I/Os

- Up to eight I/Os (GPIO_STD) supported

? Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm? SWD (serial wire debug) port

- Supports Arm? Embedded Trace Macrocell (ETM) Trace

? Data trace using SWD

? Instruction and data trace using JTAG

? Compatible with industry-standard tools

- GHS/MULTI or IAR EWARM for code development and debugging

? Packages

- 144-LQFP, 16 × 16 × 1.7 mm (max), 0.4-mm lead pitch

- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch

- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch