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DDU8C-5250中文資料DATADELAY數(shù)據(jù)手冊PDF規(guī)格書

DDU8C-5250
廠商型號

DDU8C-5250

功能描述

5-TAP, HCMOS-INTERFACED FIXED DELAY LINE

文件大小

51.2 Kbytes

頁面數(shù)量

4

生產(chǎn)廠商 Data Delay Devices, Inc.
企業(yè)簡稱

DATADELAY

中文名稱

Data Delay Devices, Inc.官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2024-11-17 19:10:00

DDU8C-5250規(guī)格書詳情

FUNCTIONAL DESCRIPTION

The DDU8C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). The total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of the total delay.

FEATURES

? Five equally spaced outputs

? Fits standard 8-pin DIP socket

? Low profile

? Auto-insertable

? Input & outputs fully CMOS interfaced & buffered

? 10 T2L fan-out capability

產(chǎn)品屬性

  • 型號:

    DDU8C-5250

  • 功能描述:

    Tapped Delay Line

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