DS21FT40中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The DS21FT40 MCM offers a high density packaging arrangement for the DS21Q44 E1 Enhanced Quad Framer. Three DS21Q44 silicon die are packaged in a Multi-Chip Module (MCM) with the electrical connections as shown in Figure 1-1. The DS21FT40 is closely related to the DS21FT44. Most of the functions of the DS21FT44 are available on the DS21FT40. The differences are listed in Table 1-1. Table 2-1 lists all of the signals on the MCM.

MULTI-CHIP MODULE FEATURES

? Twelve (12) completely independent E1 Framers in one small 27 mm x 27 mm Package

? Each Multi-Chip Module (MCM) Contains Three DS21Q44 Quad E1 Framer Die

? Each Quad Framer can be concatenated into a Single 8.192 MHz Backplane Data Stream

? 300–pin MCM 1.27 mm pitch BGA package (27 mm X 27 mm)

? Low Power 3.3V CMOS with 5V Tolerant Input & Outputs

FRAMER FEATURES

? All framers are fully independent; transmit and receive sections of each framer are fully independent

? Frames to FAS, CAS, CCS, and CRC4 formats

? Each framer contains dual two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz

? 8–bit parallel control port that can be used directly on either multiplexed or non– multiplexed buses (Intel or Motorola)

? Easy access to Si and Sa bits

? Extracts and inserts CAS signaling

? Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E-bits

? Programmable output clocks for Fractional E1, per channel loopback, H0 and H12 applications

? Integral HDLC controller with 64-byte buffers. Configurable for Sa bits or DS0 operation

? Detects and generates AIS, remote alarm, and remote multiframe alarms

? IEEE 1149.1 support