DS21Q44集成電路（IC）的電信規(guī)格書PDF中文資料

DESCRIPTION

The DS21Q44 E1 is an enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four framers that are configured and read through a common microprocessor compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer.

FEATURES

■ Four E1 (CEPT or PCM-30) /ISDN-PRI framing transceivers

■ All four framers are fully independent; transmit and receive sections of each framer are fully independent

■ Frames to FAS, CAS, CCS, and CRC4 formats

■ Each of the four framers contain dual two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz

■ 8–bit parallel control port that can be used directly on either multiplexed or non– multiplexed buses (Intel or Motorola)

■ Easy access to Si and Sa bits

■ Extracts and inserts CAS signaling

■ Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E-bits

■ Programmable output clocks for Fractional E1, per channel loopback, H0 and H12 applications

■ Integral HDLC controller with 64-byte buffers configurable for Sa bits or DS0 operation

■ Detects and generates AIS, remote alarm, and remote multiframe alarms

■ Pin compatible with DS21Q42 Enhanced Quad T1 Framer

■ 3.3V supply with 5V tolerant I/O; low power CMOS

■ Available in 128–pin TQFP package

■ IEEE 1149.1 support