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DSP56321VF220集成電路(IC)的DSP(數(shù)字信號(hào)處理器)規(guī)格書(shū)PDF中文資料

DSP56321VF220
廠商型號(hào)

DSP56321VF220

參數(shù)屬性

DSP56321VF220 封裝/外殼為196-BGA;包裝為托盤;類別為集成電路(IC)的DSP(數(shù)字信號(hào)處理器);產(chǎn)品描述:IC DSP 24BIT 220MHZ 196MAPBGA

功能描述

24-Bit Digital Signal Processor

封裝外殼

196-BGA

文件大小

1.56393 Mbytes

頁(yè)面數(shù)量

84 頁(yè)

生產(chǎn)廠商 Freescale Semiconductor, Inc
企業(yè)簡(jiǎn)稱

freescale飛思卡爾

中文名稱

飛思卡爾半導(dǎo)體官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-2-10 16:13:00

DSP56321VF220規(guī)格書(shū)詳情

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1).

The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.

Features

High-Performance DSP56300 Core

? 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O

? Object code compatible with the DSP56000 core with highly parallel instruction set

? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control

? Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memory expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

? Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals

? Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination

? Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG) test access port (TAP)

Enhanced Filter Coprocessor (EFCOP)

? Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

? Operation at the same frequency as the core (up to 275 MHz)

? Support for a variety of filter modes, some of which are optimized for cellular base station applications:

? Real finite impulse response (FIR) with real taps

? Complex FIR with complex taps

? Complex FIR generating pure real or pure imaginary outputs alternately

? A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

? Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

? Direct form 2 (DFII) IIR filter

? Four scaling factors (1, 4, 8, 16) for IIR output

? Adaptive FIR filter with true least mean square (LMS) coefficient updates

? Adaptive FIR filter with delayed LMS coefficient updates

Internal Peripherals

? Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

? Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)

? Serial communications interface (SCI) with baud rate generator

? Triple timer module

? Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    DSP56321VF220

  • 制造商:

    NXP USA Inc.

  • 類別:

    集成電路(IC) > DSP(數(shù)字信號(hào)處理器)

  • 系列:

    DSP56K/Symphony

  • 包裝:

    托盤

  • 類型:

    定點(diǎn)

  • 接口:

    主機(jī)接口,SSI,SCI

  • 時(shí)鐘速率:

    220MHz

  • 非易失性存儲(chǔ)器:

    ROM(576B)

  • 片載 RAM:

    576kB

  • 電壓 - I/O:

    3.30V

  • 電壓 - 內(nèi)核:

    1.60V

  • 工作溫度:

    -40°C ~ 100°C(TJ)

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    196-BGA

  • 供應(yīng)商器件封裝:

    196-MAPBGA(15x15)

  • 描述:

    IC DSP 24BIT 220MHZ 196MAPBGA

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
MOTOROLA
24+
BGA
2650
原裝優(yōu)勢(shì)!絕對(duì)公司現(xiàn)貨
詢價(jià)
MOTOROLA
22+
BGA
2000
原裝正品現(xiàn)貨
詢價(jià)
NXP
22+
196MAPBGA (15x15)
9000
原廠渠道,現(xiàn)貨配單
詢價(jià)
FREESCALE
17+
BGA
6200
100%原裝正品現(xiàn)貨
詢價(jià)
FREESCALE
22+23+
BGA
16917
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨
詢價(jià)
FREESCALE
BGA196
3196
正品原裝--自家現(xiàn)貨-實(shí)單可談
詢價(jià)
Freescale
22+
BGA
2200
保證有貨!質(zhì)優(yōu)價(jià)美!歡迎查詢!!
詢價(jià)
22+
5000
詢價(jià)
MOTOROLA
589220
16余年資質(zhì) 絕對(duì)原盒原盤 更多數(shù)量
詢價(jià)
NXPUSAInc.
23+
196-MAPBGA(15x15)
66800
原廠授權(quán)一級(jí)代理,專注汽車、醫(yī)療、工業(yè)、新能源!
詢價(jià)