EDI88128LPSXTB中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time.

A Low Power version with 2V Data Retention (EDI88128LPS) is also available for battery back-up opperation. Military product is available compliant to MIL-PRF-38535.

FEATURES

■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns

■ CS# and OE# Functions for Bus Control

■ 2V Data Retention (EDI88128LPS)

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

■ Organized as 128Kx8

■ Commercial, Industrial and Military Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

? 32 pin Ceramic DIP, 400 mil (Package 102)

? 32 pin Ceramic DIP, 600 mil (Package 9)

? 32 lead Ceramic ZIP (Package 100)

? 32 lead Ceramic SOJ (Package 140)

? 32 pad Ceramic LCC (Package 141)

? 32 lead Ceramic Flatpack (Package 142)

■ Single +5V (±10) Supply OperationThe EDI88128CS is a high speed, high performance, 128Kx8 megabit density Monolithic CMOS Static RAM.