EDI88130CS中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

The EDI88130CS is a high speed, high performance, 128Kx8 bits monolithic Static RAM.

An additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large multiple pages of memory are required.

The EDI88130CS has eight bi-directional input-output lines to provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data retention function for battery back-up applications.

Military product is available compliant to MIL-PRF-38535.

FEATURES

■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns

■ Battery Back-up Operation

? 2V Data Retention (EDI88130LPS)

■ CS1, CS2 & OE Functions for Bus Control

■ Inputs and Outputs Directly TTL Compatible

■ Organized as 128Kx8

■ Commercial, Industrial and Military Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

? 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)

? 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)

? 32 lead Ceramic SOJ (Package 140)

? 32 pad Ceramic Quad LCC (Package 12)

? 32 pad Ceramic LCC (Package 141)

? 32 lead Ceramic Flatpack (Package 142)

■ Single +5V (±10) Supply Operation