EVAL-ADN469XEHDEBZ開發(fā)板套件編程器的評估演示板及套件規(guī)格書PDF中文資料

EVAL-ADN469XEHDEBZ屬于開發(fā)板套件編程器的評估演示板及套件。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的EVAL-ADN469XEHDEBZ評估和演示板及套件該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗(yàn)證的實(shí)施環(huán)境中評估某些重點(diǎn)器件的性能或特性。評估方法通常有完善的文檔說明，并且視乎具體情況由評估軟件提供支持。產(chǎn)品通常由印刷電路板組成，板上已裝有重點(diǎn)器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對于數(shù)量特別多或類別獨(dú)特的器件類別(如 ADC、DAC 和開關(guān)模式電源)，評估平臺可組合為一個(gè)單獨(dú)的產(chǎn)品系列。

GENERAL DESCRIPTION

The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state with a differential input of as little as 50 mV over a common-mode voltage range of ?1 V to +3.4 V. ESD protection of up to ±15 kV is implemented on the bus pins. The parts adhere to the TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-644 LVDS devices with additional multipoint capabilities.

The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. The ADN4694E/ADN4695E are Type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe).

The parts are available as half-duplex in an 8-lead SOIC package (the ADN4690E/ADN4694E) or as full-duplex in a 14-lead SOIC package (the ADN4692E/ADN4695E). A selection table for the ADN469xE parts is shown in Table 1.