GAL6001B-30LP中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

Using a high performance E2CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24-pin, 300-mil package.

Features

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— 30ns Maximum Propagation Delay

— 27MHz Maximum Frequency

— 12ns Maximum Clock to Output Delay

— TTL Compatible 16mA Outputs

— UltraMOS? Advanced CMOS Technology

? LOW POWER CMOS

— 90mA Typical Icc

? E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

? UNPRECEDENTED FUNCTIONAL DENSITY

— 78 x 64 x 36 FPLA Architecture

— 10 Output Logic Macrocells

— 8 Buried Logic Macrocells

— 20 Input and I/O Logic Macrocells

? HIGH-LEVEL DESIGN FLEXIBILITY

— Asynchronous or Synchronous Clocking

— Separate State Register and Input Clock Pins

— Functional Superset of Existing 24-pin PAL?

and FPLA Devices

? APPLICATIONS INCLUDE:

— Sequencers

— State Machine Control

— Multiple PLD Device Integration