GS8162Z72C-133I中文資料GSI數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features

? NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM?, NoBL? and ZBT? SRAMs

? 2.5 V or 3.3 V +10/–10 core power supply

? 2.5 V or 3.3 V I/O supply

? User-configurable Pipeline and Flow Through mode

? ZQ mode pin for user-selectable high/low output drive

? IEEE 1149.1 JTAG-compatible Boundary Scan

? LBO pin for Linear or Interleave Burst mode

? Pin-compatible with 2M, 4M, and 8M devices

? Byte write operation (9-bit Bytes)

? 3 chip enable signals for easy depth expansion

? ZZ Pin for automatic power-down

? JEDEC-standard 119-, 165-, or 209-Bump BGA package