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GS84018T-180中文資料GSI數(shù)據(jù)手冊PDF規(guī)格書
GS84018T-180規(guī)格書詳情
Features
? FT pin for user configurable flow through or pipelined operation.
? Single Cycle Deselect (SCD) Operation.
? 3.3V +10/-5 Core power supply
? 2.5V or 3.3V I/O supply.
? LBO pin for linear or interleaved burst mode.
? Internal input resistors on mode pins allow floating mode pins.
? Default to Interleaved Pipelined Mode.
? Byte write (BW) and/or global write (GW) operation.
? Common data inputs and data outputs.
? Clock Control, registered, address, data, and control.
? Internal Self-Timed Write cycle.
? Automatic power-down for portable applications.
? JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Applications
The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package.
產(chǎn)品屬性
- 型號：
GS84018T-180
- 功能描述：
x18 Fast Synchronous SRAM
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
GSI |
24+ |
QFP |
35210 |
原裝現(xiàn)貨/放心購買 |
詢價(jià) | ||
GSI |
22+ |
TQFP |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價(jià) | ||
CSL |
1203+ |
QFP100 |
68 |
向鴻原裝正品/代理渠道/現(xiàn)貨優(yōu)勢 |
詢價(jià) | ||
GSI |
21+ |
QFP |
6000 |
原裝正品 |
詢價(jià) | ||
GSI |
23+ |
QFP |
10000 |
公司只做原裝正品 |
詢價(jià) | ||
GSI |
14+ |
1218 |
全新進(jìn)口原裝 |
詢價(jià) | |||
GSI |
23+ |
QFP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
GSI |
23+ |
QFP |
7300 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) | ||
GSI |
23+ |
10000 |
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價(jià)格優(yōu)勢、品種 |
詢價(jià) | |||
GSI |
2020+ |
QFP |
80000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) |
