首頁(yè) >H5TC4G83EFR-PBA>規(guī)格書列表
| 零件編號(hào) | 下載&訂購(gòu) | 功能描述 | 制造商&上傳企業(yè) | LOGO |
|---|---|---|---|---|
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAMLead-Free&Halogen-Free(RoHSCompliant) FEATURES ?VDD=VDDQ=1.35V+0.100/-0.067V ?Fullydifferentialclockinputs(CK,CK)operation ?DifferentialDataStrobe(DQS,DQS) ?OnchipDLLalignDQ,DQSandDQStransitionwithCK transition ?DMmaskswritedata-inatthebothrisingandfalling edgesofthedatastrobe ?Alla | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix | ||
4GbDDR3LSDRAM | HynixHynix Semiconductor 海力士海力士半導(dǎo)體 | Hynix |
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
HYNIX/海力士 |
1804+ |
BGA |
380 |
假一賠萬(wàn)只做原裝現(xiàn)貨實(shí)單可談 |
詢價(jià) | ||
SKHYNIX/海力士 |
23+ |
FBGA |
12500 |
全新原裝現(xiàn)貨,假一賠十 |
詢價(jià) | ||
SKHYNIX |
存儲(chǔ)器 |
BGA |
40051 |
HYNIX原裝存儲(chǔ)芯片-誠(chéng)信為本 |
詢價(jià) | ||
SK HYNIX |
新年份 |
原廠封裝 |
5000 |
原裝現(xiàn)貨質(zhì)量保證,可出樣品可開(kāi)稅票 |
詢價(jià) | ||
HYNIX |
2022+ |
BGA |
8000 |
詢價(jià) | |||
HYNIX(海力士) |
23+ |
BGA-78 |
1612 |
特價(jià)優(yōu)勢(shì)庫(kù)存質(zhì)量保證穩(wěn)定供貨 |
詢價(jià) | ||
HYNIX(海力士) |
23+ |
BGA-78 |
5768 |
百分百原裝正品,可原型號(hào)開(kāi)票 |
詢價(jià) | ||
SKHYNIX |
21+ |
BGA |
20000 |
只做正品原裝現(xiàn)貨 |
詢價(jià) | ||
HYNIX |
23+ |
BGA |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
HYNIX |
23+ |
BGA |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) |
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