HB54R1G9F2U-10B中文資料美光科技數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The HB54R1G9F2U is a 128M × 72 × 2 rank Double Data Rate (DDR) SDRAM Module, mounting 36 pieces of 256Mbits DDR SDRAM sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TCP on the module board.

Features

? 184-pin socket type package (dual lead out)

? - Outline: 133.35mm (Length) × 30.48mm (Height) × 4.80mm (Thickness)

? - Lead pitch: 1.27mm

? 2.5V power supply (VCC/VCCQ)

? SSTL-2 interface for all inputs and outputs

? Clock frequency: 133MHz/125MHz (max.)

? Data inputs and outputs are synchronized with DQS

? 4 banks can operate simultaneously and independently (Component)

? Burst read/write operation

? Programmable burst length: 2, 4, 8

? - Burst read stop capability

? Programmable burst sequence

? - Sequential

? - Interleave

? Start addressing capability

? - Even and Odd

? Programmable /CAS latency (CL): 3, 3.5

? 8192 refresh cycles: 7.8μs (8192/64ms)

? 2 variations of refresh

? - Auto refresh

? - Self refresh