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HD74HCT137FPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

HD74HCT137FPEL
廠商型號(hào)

HD74HCT137FPEL

功能描述

3-to-8-line Decoder/Demultiplexer with Address Latch

文件大小

197.84 Kbytes

頁面數(shù)量

8

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-12 23:00:00

HD74HCT137FPEL規(guī)格書詳情

Description

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features

? High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC = 2 V to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)

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HITACHI/日立
23+
NA/
3675
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HITACHI
2016+
DIP
3000
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詢價(jià)
HITACHI/日立
2023+
SOP16
6895
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HITACHI/日立
2004+
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1391
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24+
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661
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RENESAS
23+
SOP5.2
5000
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HIT/SOP5.2
1922+
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7880
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23+
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1008
全新原裝現(xiàn)貨
詢價(jià)