HYM72V1600GS-50-中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

The HYM 72V1600/10GS-50/-60 is a 128 MByte DRAM module organized as 16 777 216 words by 72-bit in a 168-pin, dual read-out, single-in-line package comprising eighteen HYB 3164400BT/BJ 16M × 4 DRAMs in 500 mil wide TSOPII or SOJ- packages mounted together with eighteen 0.2 μF ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using four BiCMOS 8-bit buffers/line drivers.

Preliminary Information

? 16 777 216 words by 72-bit ECC - mode organization

? Fast access and cycle time

50 ns access time

90 ns cycle time (-50 version)

60 ns access time

110 ns cycle time (-60 version)

? Fast page mode capability with

35 ns cycle time (-50 version)

40 ns cycle time (-60 version)

? Single + 3.3V (± 0.3V) supply

? Low power dissipation

max. 6480 mW active (-50 version)

max. 5832 mW active (-60 version)

CMOS – 108 mW standby

LVTTL – 180 mW standby

? CAS-before-RAS refresh, RAS-only-refresh

? 18 decoupling capacitors mounted on substrate

? All inputs, outputs and clock fully LVTTL & LVCMOS compatible

? 4 Byte interleave enabled, Dual Address inputs (A0/B0)

? Buffered inputs excepts RAS and DQ

? 168 pin, dual read-out, Single in-Line Memory Module

? Utilizes eighteen 16M × 4 -DRAMs and four BiCMOS 8-bit buffers/line drivers VT244A

? Two versions : HYM 72V1600GS with TSOPII-components (4 mm thickness)

HYM 72V1610GS with SOJ-components (9 mm thickness)

? 8192 refresh cycles / 128 ms with 13 / 11 addressing

? Gold contact pad

? double sided module with 38.1 mm (1500 mil) height