ICS854104I中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

General Description

The ICS854104I is a low skew, high performance 1-to-4

Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage

Differential Signaling (LVDS), the ICS854104I provides a low power,

low noise, solution for distributing clock signals over controlled

impedances of 100?. The ICS854104I accepts a differential input

level and translates it to LVDS output levels.

Guaranteed output and part-to-part skew characteristics make the

ICS854104I ideal for those applications demanding well defined

performance and repeatability.

Features

? Four differential LVDS output pairs

? One differential clock input pair

? CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

? Each output has an individual OE control

? Maximum output frequency: 700MHz

? Translates differential input signals to LVDS levels

? Additive phase jitter, RMS: 0.232ps (typical)

? Output skew: 50ps (maximum)

? Part-to-part skew: 350ps (maximum)

? Propagation delay: 1.3ns (maximum)

? 3.3V operating supply

? -40°C to 85°C ambient operating temperature

? Lead-free (RoHS 6) packaging