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IDT72281L10PFI中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

IDT72281L10PFI
廠商型號

IDT72281L10PFI

功能描述

CMOS SuperSync FIFO

文件大小

277.66 Kbytes

頁面數(shù)量

26

生產(chǎn)廠商 Integrated Device Technology, Inc.
企業(yè)簡稱

IDT

中文名稱

Integrated Device Technology, Inc.官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2024-12-29 18:06:00

IDT72281L10PFI規(guī)格書詳情

DESCRIPTION:

The IDT72281/72291 are exceptionally deep, high speed, CMOS First-InFirst-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following:

? The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency.

? The period required by the retransmit operation is now fixed and short.

? The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data.

FEATURES:

? Choose among the following memory organizations:

IDT72281 65,536 x 9

IDT72291 131,072 x 9

? Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs

? 10ns read/write cycle time (6.5ns access time)

? Fixed, low first word data latency time

? Auto power down minimizes standby power consumption

? Master Reset clears entire FIFO

? Partial Reset clears data, but retains programmable settings

? Retransmit operation with fixed, low first word data latency time

? Empty, Full and Half-Full flags signal FIFO status

? Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets

? Program partial flags by either serial or parallel means

? Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)

? Output enable puts data outputs into high impedance state

? Easily expandable in depth and width

? Independent Read and Write clocks (permit reading and writing simultaneously)

? Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- pin Slim Thin Quad Flat Pack (STQFP)

? High-performance submicron CMOS technology

? Industrial temperature range (-40°C to +85°C) is available

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IDT
23+
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9526
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IDT
24+
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83
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24+
35200
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09+
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83
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22+
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21+
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13880
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2020+
QFP
35000
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2023+
SMD
8593
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