IDT72V36102L10PF集成電路（IC）的FIFO存儲器規(guī)格書PDF中文資料

DESCRIPTION

The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored.

FEATURES

? Memory storage capacity:

IDT72V3682 – 16,384 x 36 x 2

IDT72V3692 – 32,768 x 36 x 2

IDT72V36102 – 65,536 x 36 x 2

? Supports clock frequencies up to 100MHz

? Fast access times of 6.5ns

? Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)

? Two independent clocked FIFOs buffering data in opposite directions

? Mailbox bypass register for each FIFO

? Programmable Almost-Full and Almost-Empty flags

? Microprocessor Interface Control Logic

? FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA

? FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB

? Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions)

? Available in space-saving 120-pin Thin Quad Flatpack (TQFP)

? Pin compatible to the lower density parts, IDT72V3622/72V3632/72V3642/72V3652/72V3662/72V3672

? Industrial temperature range (–40°C to +85°C) is available