IDT72V3612集成電路（IC）的FIFO存儲(chǔ)器規(guī)格書PDF中文資料

DESCRIPTION:

The IDT72V3612 is a pin and functionally compatible version of the IDT723612, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The FIFO operates in IDT Standard mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory.

FEATURES:

? Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions

? Supports clock frequencies up to 83 MHz

? Fast access times of 8ns

? Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)

? Mailbox bypass Register for each FIFO

? Programmable Almost-Full and Almost-Empty Flags

? Microprocessor interface control logic

? EFA , FFA , AEA , and AFA flags synchronized by CLKA

? EFB , FFB , AEB , and AFB flags synchronized by CLKB

? Passive parity checking on each port

? Parity generation can be selected for each port

? Available in 132-pin plastic quad flat package (PQF), or space saving 120-pin thin quad flat package (TQFP)

? Pin and functionally compatible version of the 5V operating IDT723612

? Industrial temperature range (–40°C +85°C) is available