相關(guān)元件pdf下載：sst89c58 74hc573 
reference design f sst ata-disk chip into 8051 microcontrollerapplication noteabstract: this application note introduces the hardware firmware of reference design f sst ata-disk chip sst58sd/ldxxx into sst flashflex51 sst89c54/58 (8051 compatible microcontroller).1. hardware connections: please reference to attached schematic diagram f hardware connections. sst ata-disk chip (adc) sst58sd/ldxxx only suppts one wking mode, ie. ata/ide mode, all control signals are connected based on table 2-8, page 14 on datasheet. after executed set feature comm to enable 8-bit data transfers, all higher 8 bit data bus ( d8-d15) are don’t care can be no connect. reset# (pin1) is optional, it can be tied up to vcc if not used. after power-up, adc will automatically be reset internally, it doesn’t need external reset input. but it’s a good practice to connect reset# to one of i/o pins such as p1.4, in case adc is out of control f any unknown reasons, host mcu has capability to reset adc. dasp# is connected to an emitting diode through a resist to vcc, led provides user a visibility of adc’s internal operation. when adc is active busy on operation, led will be on. please be noted that master/slave ion at csel pin won’t take effect until next reset, in other wds, if you change the jumper setting of master/slave ion, you must reset adc once. if your application system exps any other i/o data memy, please modify the reference design: (1)change cs3fx# to vcc, (2)connect the output of address decoder to cs1fx#. when both cs1fx# cs3fx# are high, adc is de-ed be stby state, all data bus are in high-z. when cs1fx# is low, adc is ed be operational. so cs1fx# acts as chip (/cs) in most common peripherals.2. firmware design guide: it’s imptant to know that ata/ide stard doesn’t permit access only one byte at a time to its media such as hdd adc, firmware must read write data sect by sect, 1 sect has 512 bytes of data, system design engineer must design data buffer to suppt rom access to adc. reference design uses the secondary block (4kbytes x 8bit) of on-chip flash in sst89c54/58 as data buffer. after power-up external reset, adc is default to be 16-bit operation. as sst89c54/58 is 8-bit mcu, firmware must enable 8-bit operation by set features comm, please reference to page 32 on datasheet. if adc is set as slave, other than master, you need to change the bit4 in drive/head register to be 1 when writing comm to adc, see page 17 on datasheet. after power-on reset, adc will be ready to read / write operation after 200ms (typical), 500ms (maximum), see page 1 under start up time in features on datasheet.3. conclusion:it’s easy to modify this reference design to any other embedded controllers as long as you follow above design guidelines.4. schematic diagram:5. 8051 source code:; all comms suppted by adc.chkpwr equ 0e5h ; 98hdiagnostic equ 90hfmat equ 50hidentify equ 0echidle equ 0e3h ; 97hidleimm equ 0e1h ; 95hinitialize equ 91hreadbuf equ 0e4hreadlong equ 22h ; 23hreadmulti equ 0c4hreadsctr equ 20h ; 21hreadverify equ 40h ; 41hrecalibrate equ 10h ; 1xhseek equ 70h ; 7xhsetfeature equ 0efhsetmulti equ 0c6hsleep equ 0e6h ; 99hstby equ 0e2h ; 96hstbyimm equ 0e0h ; 94hwritebuf equ 0e8hwritelong equ 32h ; 33hwritemulti equ 0c5hwritesctr equ 30h ; 31hwriteverify equ 3ch;=============================================================; adc drive register set definitionsdata_reg equ 8000h ; data register f read / writeerr_reg equ 8001h ; err register, read onlyfeatures equ 8001h ; features register, write onlysectr_cnt equ 8002h ; sect count register ( r / w )sectr_no equ 8003h ; sect number register, lba0:7 ( r / w )cylinder_low equ 8004h ; cylinder low register lba8:15 ( r / w )cylinder_hi equ 8005h ; cylinder high register lba16:23 ( r / w )drv_head equ 8006h ; drive head register ( r / w ) status equ 8007h ; status register, read onlycomm equ 8007h ; comm register, write onlyalt_status equ 4006h ; alternate status register, read only, ; reading alt_status doesn't clear interrupt pending flag. not used in this demo.device_ctrl equ 4006h ; device control register, write only. not used in this demo.drive_addrs equ 4007h ; drive address register, read only. not used in this demo.;=================================================================; sst flashflex51 microcontroller related sfr's definitionsfcf data 0b1h ; superflash configurationsfcm data 0b2h ; superflash commsfal data 0b3h ; superflash address lowsfah data 0b4h ; superflash address highsfdt data 0b5h ; superflash datasfst data 0b6h ; superflash statuswdtc data 0c0h ; watchdog timer controlwdtd data 86h ; watchdog timer data/reload;=================================================================; constant definitionflashaddrs equ 0f800h ; start address to ste data from adc;=========================================== g 0000h ljmp start g 0100hstart: clr p1.4 ; reset adc nop nop nop nop setb p1.4 mov r4, #5 ; delay 0.5 secondloadr5: mov r5, #200 ; delay 0.1 secondloadr6: mov r6, #250 ; delay 0.5ms f 12mhz crystal djnz r6, $ djnz r5, loadr6 djnz r4, loadr5 acall enable8bit ; first of all, enable 8 bits operation!;======================================== l sfcf, #40h ; iapen=1 mov sfah, #high(flashaddrs) mov sfal, #low(flashaddrs) mov b, #8 ; erase 8 sects (512 bytes) ;========================================erase: mov sfcm, #0bh ; sect erase! acall done? mov a, sfal add a, #64 ; 64 bytes / sect in block 1 of sst89c54/58 mov sfal, a mov a, sfah addc a, #0 mov sfah, a djnz b, erase anl sfcf, #0bfh ; disable iap ;======================================== main: acall write_sctr acall read_sctr acall compare jb f0, fail clr p1.4 ; indicates successful operations. setb p1.5 sjmp $fail: clr p1.5 ; flags failed comaprison. setb p1.4 sjmp $;========================================function: acall busy mov dptr, #sectr_cnt mov a, r2 ; r2 is sect count movx @dptr, a mov dptr, #sectr_no mov a, r3 ; r3 contains lba0:7 movx @dptr, a mov dptr, #cylinder_low mov a, r4 ; r4 contains lba8:15 movx @dptr, a mov dptr, #cylinder_hi mov a, r5 ; r5 contains lba16:23 movx @dptr, a mov dptr, #drv_head mov a, r6 ; r6 contains lba24:27 anl a, #00001111b l a, #11100000b ; bit4=0 as master, 1 as slave; bit6=1, enable lba. movx @dptr, a mov dptr, #comm mov a, r7 ; r7 is comm code. movx @dptr, a ret;========================================busy: mov dptr, #status movx a, @dptr jb acc.7, busy jb acc.0, errs; jnb acc.6, busy clr a ; acc=0 when successful clr c ; c=0, adc is not busy (busy=0) no err (err=0) ret ; is ready to accept comms (rdy=1)errs: mov dptr, #err_reg movx a, @dptr setb c ; c=1 flags err codes contained in acc register ret;========================================waitdrq: mov dptr, #status movx a, @dptr jb acc.7, waitdrq ; if busy=1, then waitdrq jnb acc.3, waitdrq ; if drq=0, then waitdrq jb acc.0, errs ; if err=1, then read errs code set flag c; jnb acc.6, waitdrq clr a clr c ; c=0, adc is busy=0, drq=1, err=0. ret ;========================================done?: mov a, sfst jb acc.2, done? ret;========================================enable8bit: acall busy mov dptr, #features mov a, #01h ; enable 8 bit data transfer movx @dptr, a mov dptr, #drv_head mov a, #11100000b ; bit4=0 as master, 1 as slave ; bit6=1, enable lba movx @dptr, a mov dptr, #comm mov a, #setfeature ; #0efh movx @dptr, a ret;========================================write_sctr: mov r2, #1 ; write 1 sect at a time. mov r3, #0ah ; suppose lba to be 000000ah mov r4, #0 mov r5, #0 mov r6, #0 mov r7, #writesctr acall function acall waitdrq acall write512 ret;========================================write512: mov r0, #high(message) ; get the higher address of message mov r1, #low(message) ; get the lower address of message mov r7, #2 ; 512 bytes = 2 * 256 mov b, #0 write: mov dph, r0 ; get the address mov dpl, r1 clr a movc a, @a+dptr ; get the data in message inc dptr ; point to next byte in message mov r0, dph ; save the address mov r1, dpl mov dptr, #data_reg ; point to adc movx @dptr, a ; write 1 byte data into adc djnz b, write djnz r7, write ; write all 512 bytes to adc ret;========================================read_sctr: mov r2, #1 ; read 1 sect at a time. mov r3, #0ah ; suppose lba to be 000000ah mov r4, #0 mov r5, #0 mov r6, #0 mov r7, #readsctr acall function acall waitdrq acall read512 ret;========================================; read 1 sect of 512 bytes data write into flash on chip of sst flashflex51 mcuread512: mov r7, #2 ; 512 bytes = 2 * 256 mov b, #0 mov dptr, #data_reg mov sfah, #high(flashaddrs) mov sfal, #low(flashaddrs) l sfcf, #40h ; set iapen=1 to enable iapread: movx a, @dptr ; read 1 byte data from adc mov sfdt, a ; program into on-chip flash mov sfcm, #0eh ; issue byte-program comm acall done? ; wait until done mov a, sfal ; adjust the address of flash add a, #1 mov sfal, a mov a, sfah addc a, #0 mov sfah, a djnz b, read djnz r7, read anl sfcf, #0bfh ; disable iap ret ;========================================compare: mov dptr, #message ; point to message mov sfah, #high(flashaddrs) mov sfal, #low(flashaddrs) l sfcf, #40h ; iapen=1 clr f0 mov r7, #2 mov b, #0verify: clr a movc a, @a+dptr ; get iginal data in message inc dptr mov sfcm, #0ch ; issue byte-verify comm nop xrl a, sfdt ; sfdt contains data in flash, these data come from adc jz skip setb f0 ; set flag f0 (psw.5) if any discrepancy.skip: mov a, sfal ; increase the address of flash add a, #1 mov sfal, a mov a, sfah addc a, #0 mov sfah, a djnz b, verify djnz r7, verify anl sfcf, #0bfh ; disable iap ret ;========================================================================message: db "this demo program demonstrates how easy to design " db "sst ata-disk chip into sst flashflex51 embedded microcontroller. " db "after you underst how to use the basic writesect readsect " db "functions, it's easy to try any others." db "the hardware connection between adc mcu is also very simple," db "just like you exp any i/o data memy in your application system. " db "after power-on, adc is default to be 16 bit operation as all eide " db "stards, firmware needs enable 8 bit operation befe " db "further write / read operation." end
