OVERVIEW

ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

GENERAL DESCRIPTION

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally confgured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits.

FEATURES

? Clock frequency: 200, 166, 143, 133 MHz

? Fully synchronous; all signals referenced to a positive clock edge

? Internal bank for hiding row access/precharge

? Single 3.3V power supply

? LVTTL interface

? Programmable burst length: (1, 2, 4, 8, full page)

? Programmable burst sequence: Sequential/Interleave

? Self refresh modes

? 4096 refresh cycles every 16ms (A2 grade) or 64ms (Commercia, Industrial, A1 grade)

? Random column address every clock cycle

? Programmable CAS latency (2, 3 clocks)

? Burst read/write and burst read/single write operations capability

? Burst termination by burst stop and precharge command

IS45S32200E-7BLA2屬于集成電路（IC） > 存儲器。北京矽成半導體有限公司制造生產(chǎn)的IS45S32200E-7BLA2存儲器存儲器是集成電路上用作數(shù)據(jù)存儲設備的半導體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。