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ISPLSI1024EA-200LT100中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書
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ISPLSI1024EA-200LT100規(guī)格書詳情
Description
The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP).
Features
? HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 48 I/O Pins, Two Dedicated Inputs
— 144 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
? NEW FEATURES
— 100 IEEE 1149.1 Boundary Scan Testable
— ispJTAG? In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports
MixedVoltage Systems (VCCIO Pin)
— Open-Drain Output Option
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 200 MHz Maximum Operating Frequency
— tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
? IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-Market
and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
? ispDesignEXPERT? – LOGIC COMPILER
AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER?
— PC and UNIX Platforms
產(chǎn)品屬性
- 型號:
ISPLSI1024EA-200LT100
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件
- RoHS:
否
- 制造商:
Lattice
- 存儲類型:
EEPROM
- 大電池數(shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
LATTICE |
2020+ |
PGA |
80000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價 | ||
ALTERA/阿爾特拉 |
24+ |
PLCC |
45 |
原裝現(xiàn)貨假一賠十 |
詢價 | ||
LATTICE |
21+ |
PGA |
10000 |
原裝現(xiàn)貨假一罰十 |
詢價 | ||
ALTERA |
23+ |
PLCC-84 |
1220 |
專業(yè)優(yōu)勢供應(yīng) |
詢價 | ||
LatticeSemiconductorCorp |
23+ |
100-TQFP(14x14) |
66800 |
原廠授權(quán)一級代理,專注汽車、醫(yī)療、工業(yè)、新能源! |
詢價 | ||
LATTICE |
602 |
原裝正品現(xiàn)貨庫存價優(yōu) |
詢價 | ||||
ALTERA |
23+ |
PLCC-84 |
4500 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售 |
詢價 | ||
Lattice |
23+ |
PLCC84 |
7000 |
絕對全新原裝!100%保質(zhì)量特價!請放心訂購! |
詢價 | ||
LATTICE |
24+ |
QFP |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
LATTICE |
23+ |
DIP |
5000 |
原裝正品,假一罰十 |
詢價 |