ISPLSI2192VE-225-LB144中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The ispLSI 2192VE is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100 IEEE 1149.1 Boundary Scan Testable. The ispLSI 2192VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

Features

? SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

— 8000 PLD Gates

— 96 I/O Pins, Nine or Twelve Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Pinout Compatible with ispLSI 2096V and 2096VE

? 3.3V LOW VOLTAGE ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

? HIGH PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 225MHz* Maximum Operating Frequency

— tpd = 4.0ns* Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

? IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP?) Using Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE

? THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER?

— PC and UNIX Platforms