K4H511638G-LC/LCC中文資料三星數(shù)據(jù)手冊(cè)PDF規(guī)格書

General Description

The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

Key Features

? VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333

? VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400

? Double-data-rate architecture; two data transfers per clock cycle

? Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)

? Four banks operation

? Differential clock inputs(CK and CK)

? DLL aligns DQ and DQS transition with CK transition

? MRS cycle with address key programs

-. Read latency : DDR266(2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

? Data I/O transactions on both edges of data strobe

? Edge aligned data output, center aligned data input

? LDM,UDM for write masking only (x16)

? DM for write masking only (x4, x8)

? Auto & Self refresh

? 7.8us refresh interval(8K/64ms refresh)

? Maximum burst refresh cycle : 8

? 66pin TSOP II Lead-Free & Halogen-Free package

? RoHS compliant