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K4T1G084QC中文資料三星數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

K4T1G084QC
廠商型號(hào)

K4T1G084QC

功能描述

1Gb C-die DDR2 SDRAM Specification

文件大小

485.58 Kbytes

頁(yè)面數(shù)量

26 頁(yè)

生產(chǎn)廠商 Samsung semiconductor
企業(yè)簡(jiǎn)稱(chēng)

Samsung三星

中文名稱(chēng)

三星半導(dǎo)體官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-11-17 22:59:00

K4T1G084QC規(guī)格書(shū)詳情

1Gb C-die DDR2 SDRAM Specification 60FBGA & 84FBGA with Pb-Free

The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications.

The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.

Key Features

? JEDEC standard 1.8V ± 0.1V Power Supply

? VDDQ = 1.8V ± 0.1V

? 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/

pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/

sec/pin

? 8 Banks

? Posted CAS

? Programmable CAS Latency: 3, 4, 5, 6

? Programmable Additive Latency: 0, 1, 2, 3, 4, 5

? Write Latency(WL) = Read Latency(RL) -1

? Burst Length: 4 , 8(Interleave/nibble sequential)

? Programmable Sequential / Interleave Burst Mode

? Bi-directional Differential Data-Strobe (Single-ended datastrobe is an optional feature)

? Off-Chip Driver(OCD) Impedance Adjustment

? On Die Termination

? Special Function Support

- PASR(Partial Array Self Refresh)

- 50ohm ODT

- High Temperature Self-Refresh rate enable

? Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C

? All of Lead-free products are compliant for RoHS

產(chǎn)品屬性

  • 型號(hào):

    K4T1G084QC

  • 制造商:

    SAMSUNG

  • 制造商全稱(chēng):

    Samsung semiconductor

  • 功能描述:

    1Gb C-die DDR2 SDRAM Specification

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